Overcome Power, Size and Cost when Developing Optimized '4G' Chipsets for Handhelds - Mobile Handset DesignLine

Overcome Power, Size and Cost when Developing Optimized 4G Chipsets for Handhelds
Mobile Handset DesignLine
April 23, 2008

Eran Eshed, Altair Semiconductor

The combination of broadband and mobility promises to revolutionize the wireless Internet user-experience in a similar manner that such broadband technologies as DSL and cable modems transformed the wired Internet. Mobile WiMAX and 3GPP LTE (Long Term Evolution), or "4G" technologies, are expected to lead this mobile broadband revolution--the former is already in early deployment stages with the latter following on its heels.

The tools that will drive this revolution--and the demand for the services that are expected to entice consumers to pay an extra thirty or forty dollars a month--will be personal, handheld portable or mobile devices. This represents a true paradigm shift from the traditional laptop and hotspot combination to an anywhere personalized handheld device. Apple's iPhone is but a mere glimpse into the types of devices consumers can expect to see launching and driving the adoption of these advanced broadband services on-the-go.

Chipsets for integration into handheld devices have always represented the state-of-the-art in terms of semiconductor power consumption, form factors and integration levels. Among those three categories, power consumption reduction is arguably the most significant challenge faced by handset and handheld device manufacturers because its impact on battery time and subsequently on user experience is direct and immediate. The bad news for these manufacturers is that 4G chipsets that receive and transmit wideband signals and employ advanced smart antenna techniques such as MIMO (Multiple In Multiple Out), require dramatically higher processing power compared to traditional cellular technologies. The implications of this high processing requirement are micro-processors and DSPs (digital signal processors) that have to be clocked at much higher frequencies--a fact that has a linear effect on the power consumption. The good news for innovative chip companies is that a large power-consumption capability vacuum was created by this shift from narrowband to broadband mobility, and those companies that manage to overcome these challenges will have established a strong and sustainable competitive advantage.

This article will discuss the dimensions that should be addressed by 4G chip developers to minimize the power consumption, size and cost of their solutions.

The System Dimension
A mobile broadband solution includes a few key components:

    * Baseband processor--responsible for the processing of the physical (PHY) and Media Access Control (MAC) protocol layers
    * RF transceiver--responsible for down-converting the GHz radio frequency signals into lower frequencies that the baseband processor can handle, and up-converting in the opposite direction
    * Power amplifier (PA)--responsible for amplifying the transmitted signals to extend the range of transmission

Too often suppliers of one or two components of this solution tend to focus on optimizing their respective products and fail to consider the system level aspects of reducing the power consumption. Using Mobile WiMAX as an example, several chip suppliers develop both the baseband and RF components of the system--giving them an advantage over pure play baseband or RF players. None of these suppliers, however, also develops the PA, which belongs to a very different semiconductor discipline. Tight cooperation at the specification and design phases between these companies can yield surprisingly efficient system level solutions. Such cooperation should be driven by baseband players, as most of the "intelligence" in the system resides in this processor, and the potential power savings achieved by smart and innovative baseband design extend well beyond the power consumption of the baseband chip itself.

The Architecture Dimension
A typical approach by chip suppliers in emerging markets such as 4G is to attempt to maximize the total addressable market while minimizing the R&D investment. This can be achieved by developing a single chip product or product line that is intended to serve multiple device segments--such as desktop modems, PC cards, USB dongles, handsets and handheld devices.

It's a viable methodology considering the significant investment required to bring a chip to the market and the expected limited shipments in a new market, but ultimately yields semiconductor products that are capable of functioning in any of the aforementioned devices, however significantly compromise on power consumption, size, performance and cost.

In order to highlight this point, it is useful to consider an example taken from the mobile WiMAX world. Most mobile WiMAX baseband processors were designed to fit into PC card applications. These applications require the attachment of a large and external memory to the chip, as well as the incorporation of interfaces such as PCI Express or USB. In a handheld application, these elements are not needed, but the power consumption, cost and footprint penalty are still incurred. What might seem a fairly simple task of creating optimized derivatives of the chip for different applications is in fact a complete re-design of the product, as the level of optimization required for battery-operated handheld devices dictates a completely different software/hardware partitioning. The same argument applies to the RF transceiver and PA, which need to be optimized for the application they are intended to serve.

"One size fits all" solutions by nature are non-optimized.

The Chip Dimension
After having looked at the system level aspects of the optimization, each of the three components in the system require individual optimization for power, size and cost. The most complex component is the baseband processor, which is typically a mixed-signal SoC that includes both digital and analog content, and runs firmware on integrated microprocessors--each subject to thorough optimization. The optimizations include good practice ASIC design, as well as cutting edge non-traditional signal processing approaches and architectures that on one hand ensure minimal power consumption, and on the other provide the adequate level of flexibility required for a new communications standard. The RF transceiver and PA consume most of the power consumption in the system, and also require individual optimization and tuning to increase efficiency and minimize power and size.

Summary
In this short article, we provided a sample of the dimensions of a mobile broadband system that chip developers must address in order to optimize their solutions for power consumption, size and cost. These three elements are essential parameters in the success of the technology in a mass adoption scenario. We also addressed the synergistic effect that optimization allows across the three elements of the system--baseband processor, RF transceiver and power amplifier.

About the Author
Eran Eshed is a co-founder and vice president of marketing and business development at Altair Semiconductor, a 4G chip company. Previously, Eshed worked at Texas Instruments (TI) as director of cable modem marketing. Prior to that, he held various hardware and silicon development and management positions, at TI and at Libit Signal Processing. Eshed holds a B.Sc. in Electrical Engineering from the Tel Aviv University. He can be reached at: eran@altair-semi.com.